Brain-Computer Interface (BCI)-based Systems (2018-2020):


This research thread investigates the design of computer systems that interface with the human brain through Electroencephalography (EEG). One specific application is a BCI Speller, which allows users with diminished (or no) motor-skills to spell words using a BCI speller.


Publications : UEMCON18-BCI   

Semi-Autonomous UAV Swarms (2018-2020):


This research thread investigates the design of an Unmanned Aerial Vehicle (UAV) swarm (consisting of n  UAVs) that is capable of semi-autonomous flight. This research breaks downs into three sub-threads: i) Building a multi-tier computational/communication architecture using the embedded devices within the swarm members to allow 3D Site Reconstruction, in which a high-resolution image is formed by stitching together the individual images received from UAV members,    ii) Semi-Autonomous Control, which investigates a set of algorithms to keep the autonomous swarm members in close proximity of the controlled one; in this way, a team of pilots control only a single UAV and the other UAVs at the periphery of the controlled one follow the others autonomously, and iii) Continuous Energy Replenishment, which studies a mechanism to allow perpetual flight by allowing the UAVs to continuously fly to the nearest charge station, replenish their energy, and swap with an energy-depleted UAV.


Publications : UEMCON18-UAV   

Smart City (2016-2019):


My Smart City project breaks down into multiple sub-categories: i) IoT-Based (Internet-Of-Things) Intelligent Sensing, where the IoT sensor networks capture, concentrate and transmit pre-processed data into the cloud. ii) Crowd-sensing and Crowd-Sourcing, where the data that is directly sensed or captured from the IoT sensor network is transported/pre-processed by a volunteering group of smartphone users. iii) Compute-Intensive Cloud Analytics, where the data that is transmitted to the cloud is analyzed through Data Mining algorithms and the results are used to engage a set of actuators.


Publications : MCAS16              ACCESS16     CCSNA16       ACCESS17         MWSCAS17-SC   
                       MWSCAS17-WI    SOCC17        MCAS17        ACCESS17-GM    SENSORS17   

Digital Health (D-Health) (2015-2019):


My research in the D-Health field encompasses the following sub-fields: i) Medical Data Acquisition, where the medical data is acquired from either the sensors on a human body (e.g., Body Area Networks). ii) Data Pre-Processing, Acceleration and Aggregation, where the data from multiple sensors is aggregated, pre-processed and transmitted to the cloud via the help of an intermediate device such as a cloudlet. iii) Compute-Intensive Cloud Processing, where the data that is transmitted to the cloud is analyzed through statistical inference algorithms and decision support is provided to the doctors. This area of my research makes use of heavy GPU processing, as well as machine learning algorithms.


Publications : ICCD13         IGI14-MED    ANEC14      CCSNA14-HE    IGI15-BP      IGI15-DH   
                       IGI15-FHE     IGI15-OP      SCC15        GC15               ACCESS15    HR16   
                       IJSC16          TCBB16        ISCC16       MC16              CSUR19        ACCESS18-DH
                       JEC19           JIOT19   

Supercapacitor-Based Cyber Physical Systems (2012-2017):


Intelligent field systems like highway traffic management or area surveillance require substantial data collection in the field. Processing of this data in the field requires processing power that is not attainable via low-powered embedded devices. Recent advances in GPU technology afford embedded devices powered by advanced processors such as TEGRA3 to process the acquired data in the field. Intelligent field systems are traditionally powered by self-sustainable power sources such solar panels and the excess energy generated by the power source is buffered in rechargeable batteries.

As an alternative to rechargeable batteries, our research focuses on the application of a different buffering mechanism using super-capacitors. Super-capacitors have near-infinite lifetime and are manufactured using significantly more environmentally-friendly materials as compared to rechargeable batteries. Also, their remaining energy can be estimated with better than 1% accuracy. This feature permits a new set of energy-aware applications by using super-capacitors. Despite these advantages, super-capacitors only have a tenth of the energy density that of rechargeables. Our research is centered around building field systems that can be powered via solar panels by using super-capacitors as the storage medium. Our research goal is to create a new class of environmentally-friendly field systems that amass a significant compute-capability, which are virtually maintenance-free and can be deployed in areas where maintenance is of significant premium.


Publications : SOCC12-SC    ICASSP14       SOCC14              CRC15-SC    CRC15-EN    POWER15   
                       ACCESS16     URCS-TR16     MWSCAS17-SC     SOCC17       MCAS17   

NSF Award   :

Project Site  :

Video            : NSF-CNS-1239423-2014

Secure Medical Cloud Computing Using Homomorphic Encryption (2013-2016):


An important piece of transitioning the US Healthcare into the digital era involves enabling the healthcare organizations (HCO) the use cloud resources, such as Amazon Web Services (AWS). While the HCOs will welcome this opportunity, data privacy concerns prevent wide adoption. This research initiative investigates the possibility of using Fully Homomorphic Encryption (FHE) to perform medical computation in the cloud, so, the Protected Health Information (PHI) is not observed during the computation. While the concept is very attractive from a theoretical perspective, it comes with extreme challenges in terms of computation speed and storage requirements. Although it might take many years for FHE to become a reality, this research  initiative explores the possible operations that are feasible within the following half decade.


Publications : ICCD13    IGI14-MED    ANEC14    CCSNA14-HE    IGI15-BP    IGI15-FHE    TCBB16   

MOCHA : MObile Cloud-based Hybrid Architecture (2011-2015):


Simultaneous advances in the sensory and compute-capabilities of mobile devices and cloud computing have brought the state-of-the-art to a point, where compute-intensive real-time applications can now be executed on mobile platforms utilizing the cloud. Example applications include 1) cloud-assisted real-time surgery, 2) real-time face detection and recognition at an airport, 3) object-recognition help in the battlezone, to name a few. In this research, we study the feasibility of running such compute-intensive applications on mobile devices by utilizing the cloud in real-time. We also research their interaction with Big Data located in the cloud.


Publications : SPIE12        ISCC12       IGI13          IGI14-BD         CLOUD14    CCSNA14-AX   
                       IGI15          IGI15-VM    IGI15-AX     IGI15-FRGPU    CNET15      CCSNA15    

Project Site  : MOCHA Project Website

Low Energy-Consumption Content Addressable Memory (CAM) (2011-2013):


This research departs from the vision that, the human brain consists of a whole bunch of Content Addressable Memories (CAMs), say, billions or more. The reason we haven't gotten close to certain capabilities (e.g., face recognition) of the human brain is because: a) we haven't been able to build energy-efficient CAMs which will make it feasible to utilize many more orders of magnitude more CAMs, b) we haven't been able to completely figure out what needs to be stored as the Content. While there are plenty of researchers researching (b), our focus is building energy efficient CAMs, so, a completely different set of algorithms utilizing three to five orders of magnitude bigger CAMs can be enabled, which are specialized in unusual search functions.


Publications : SOCC12-PB

Utilizing STT-MRAM to design a low-power microprocessor (2009-2010):


Spin Transfer Torque Magnetoresistive RAM (STT-MRAM) is a CMOS-compatible non-volatile memory, amassing superior circuit properties, such as low-leakage and low read energy due to its lower read voltage as compared to SRAM. Prior research establishes STT-MRAM as a good L2 or L3 cache replacement alternative. STT-MRAM has been shown to improve energy consumption due to the aforementioned favorable operational characteristics. L2 and L3 caches are good candidates for the utilization of STT-MRAM due to their low activity factors. In such low activity structures of a microprocessor, the primary advantage of STT-MRAM, i.e., its reduced area, plays an important role in reducing bitline and matchline dynamic energy consumption. Alternatively, the primary disadvantages of STT-MRAM, i.e., its high write energy and high write latency, are subdued due to the lower write activity.


In this research, we study STT-MRAM for use in other parts of a microprocessor, such as L1D and L1I cache, ALU, FPU, LDQ, STQ, BTB, PC, decoder, memory controller, and register file. This integration is realized by utilizing STT-MRAM in two different forms: Look up tables (LUTs) are employed to replace general logic, and standard STT-MRAM constructions are used for memory-like architectures. It is shown that, STT-MRAM can provide a much broader replacement alternative than the standard L2$ and L3$.


Publications : ISCA10

Retiming with Circuit Non-idealities (1993-1997):


Retiming process achieves a reduction in the clock period of a synchronous circuit by relocating the synchronizing elements (e.g., flip flops) to transform the original circuit into a functionally equivalent one, in which the critical path delay (i.e., the clock period) is reduced due to the lower worst case path delay. This technique assumes zero or negligible delays for three of the circuit components : 1) interconnect between the synchronizing elements, 2) propogation delays between synchronizing elements, 3) clock delay difference between two sequentially-adjacent synchronizing element (i.e., clock skew).


In this research, we introduce Register Electrical Characteristics (REC) which quantify these electrical non-idealities. We attaches RECs to the edges of the graph representing the synchronous circuit. This permit extension of the existing retiming algorithms to incorporate RECs. However, certain important newly developed characteristics, such as path delay monotonicity has to be considered to successfully achieve this. By incorporating these circuit parameters, a much more accurate end result can be obtained from the retiming process, thereby making it more applicable to industrial ASIC design processes.



Publications : ISCAS93   ASIC94   ICCAD94   ISCAS95   TCAD97     Soyata Ph.D. Thesis